1. Field of the Invention
The present invention relates to a semiconductor device and a process of producing same, particularly to a semiconductor memory device having a difference in height between a memory cell area and a peripheral circuit area surrounding the memory cell area.
2. Description of the Related Art
Highly integrated DRAMs tend to have the capacitor electrode of a greater height to ensure a greater storage capacity. Capacitors are provided only in the memory cells but not in the surrounding circuit areas, causing increase in the difference between heights of the memory cell area and the surrounding circuit area. The increased integration or refinement involves the narrowing of conductor wirings running above the memory cell area and the surrounding circuit area. This reduces the focus depth allowance upon exposure for forming the conductor pattern. The above-mentioned increase in the height difference further reduces the focus depth allowance.
This phenomenon is fully described in Japanese Patent Application No. 3-285088 by the same assignee, in which the present inventors proposed to design memory cells so as to be covered by the focus depth allowance of the exposing apparatus. This proposal, however, uses an ECC (error correction code) to suppress the natural .alpha.-rays soft error and the ECC unavoidably causes a drop in the working speed of the device.
An SRAM (static random access memory) cell composed of MOS transistors is expressed as an equivalent circuit as shown in FIG. 1, containing driving MOSFETs t11 and t12, loading MOSFETs t21 and t22, and transfer MOSFETs t31 and t32.
The driving MOSFETs t11 and t12 have channel regions formed in the bulk body of a semiconductor substrate and the loading MOSFETs t21 and t22 have channel regions formed in polycrystalline semiconductor layer on the semiconductor substrate.
FIG. 2A shows a sectional view of the MOSFETs in the portion enclosed by the broken line of FIG. 1.
An active region X surrounded and defined by a selectively oxidized layer 382 on a semiconductor substrate 381. The driving MOSFET t11 has a gate electrode 383 formed on the substrate 381 in the active region X with a gate insulating layer 384 interposed between the electrode 383 and the substrate 381. The gate electrode 383 has one end stepping over the selectively oxidized region 382 and connected to an impurity-doped region 385.
Above an insulating layer 386 covering the gate electrode 383, a lower gate electrode 387, a polycrystalline semiconductor layer 388 and an upper gate electrode 389 are formed to compose a loading MOSFET t22, with insulating layers 390 and 391 interposed between the lower electrode 387 and the Semiconductor layer 388 and between the semiconductor layer 388 and the upper insulating layer 389, respectively.
The polycrystalline semiconductor layer 388 has a channel region with introduced impurities on the both sides thereof to define source/drain regions. The two gate electrodes (or double gates) 387 and 389 are connected to the source/drain regions of the loading MOSFET t21 located on the substrate 381.
A contact hole 392 is formed through the insulating layers 386, 390 and 391 and through the polycrystalline semiconductor layer 388, which are located on the gate electrode 383 stepping over the selectively oxidized layer 382. The contact hole 392 has a side wall and a bottom surface which are coated with a conductive layer 393 having a U-shaped section. This arrangement connects the gate electrode 383 of the driving MOSFET t11 to one of the source/drain regions of the loading MOSFET t22.
The impurity-doped region 385 defined in the active region X is connected to one end of the gate electrode 383 of the driving MOSFET t11 and is connected to one of source/drain regions 394 and 395 of the transfer MOSFET t31. Gate electrode 396 of the transfer MOSFET t31 is formed on the semiconductor substrate 381 with a gate insulating layer interposed therebetween.
An insulating layer 397 covers the SRAM area Y and the surrounding area Z.
As described above, the loading MOSFET t22 has two gate electrodes 387 and 389 and the semiconductor layer 388, which are formed on the semiconductor substrate 381, to form a multiple-layered structure, so that the SRAM cell area Y is higher than the surrounding circuit area Z to form a step of height "d".
To minimize the step height "d", a BPSG (borophosphosilicate glass) layer 397 is formed all over the substrate and is then heated to relfow, as shown in FIG. 2B.
This cannot provide sufficient flattening where the height of SRAMs tends to increase more and more. For example, the step height is not reduced sufficiently when a capacitor "Q" is formed on the loading MOSFET t22 in order to avoid .alpha.-rays soft errors, as shown in FIG. 3A.
The capacitor "Q" is formed by increasing the height of the space for the conductive layer 393 (FIG. 2A) which connects the gate electrode 383 of the driving MOSFET t11 to the source/drain regions of the loading MOSFET t22, forming in that space a storing electrode "SN" in the form of a fin, coating the electrode "SN" with a dielectric layer "DL" and forming a counter electrode "CP" on the layer "DL".
It is usually necessary to form contact holes simultaneously in both the SRAM cell area Y and surrounding circuit area Z or to form wiring running over both areas Y and Z, by exposing a photoresist 398 as shown in FIG. 3B. The focus depth may be smaller than the height "d" of such a large step, causing degradation of the precision of patterning.
In "Semiconductor World", December 1991, p.186, Oowada pointed out the importance of the reduction of the step height in the multiple layered wiring technology, particularly in logic ICs. This problem is common to the height difference between the memory cell and the surrounding circuit. It should be noted, however, that the height difference in logic ICs is caused by a random wiring, so that the distribution of height difference is more complicated than that in memory cells. Oowada did not suggest a solution therefor.
FIGS. 4A, 4B and 4C show a commonly known process for flattening of the wiring steps, as can be seen from "Solid State Technology", Nov. 1991, p.67-71, for example.
Referring to FIG. 4A, a wiring 111 is formed on a substrate 110 and is then covered with an insulating layer 112. The insulating layer 112 stands out in the portion of a smaller spacing of the wiring 111 than in the portion of a greater spacing. A resist pattern 113 is then formed on the insulating layer 112 in the portion with a wiring spacing greater than a certain value.
Referring to FIG. 4B, etching of the insulating layer 112 is carried out by utilizing the resist 113 as a mask to reduce the height of insulating layer 112 in the portion with a smaller spacing of the wiring 111. This etching must be precisely controlled, because an excessive etching causes an abnormal step and an insufficient etching causes an incomplete flattening.
Referring to FIG. 4C, after the resist 113 is removed, an upper insulating layer 114 is formed to complete the flattening necessary for an overlying wiring layer to be formed.
The insulating layers 112 and 114 may be far more effective when formed of composite SOG (spin-on-glass)/CVD-oxide layers than when formed of a CVD-oxide layer alone.
Another processes are known, in which a complete flattening of the wiring steps is effected by the combined use of a special polymer or film and an etching back technique, as is proposed by Numazawa et al. in the proceedings of "SEMI technology symposium", p.245-255 and by D. Wang et al., ibid, p. 257-265.
The above-recited conventional technologies, however, were intended to cover all the steps caused by a random wiring and having a complicated pattern, in which the following substantial problems are remaining:
1) A high precision etching technique is necessary; PA1 2) The use of a special polymer is not only a disadvantage in itself but also necessitates etching control to avoid leaving remains of such a polymer; and PA1 3) An etching control for simultaneously etching-back layers of different materials is necessary. PA1 a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween; PA1 a first conductive layer covering the memory cell area and extending onto the boundary area; PA1 a first insulating layer covering the surrounding circuit area and part of the extended portion of the first conductive layer; PA1 a second insulating layer covering the first insulating layer and the first conductive layer; PA1 a throughhole formed through the first and second insulating layers; and PA1 a second conductive layer electrically connected with another conductive layer via the throughhole and extending from the memory cell area to the surrounding circuit area. PA1 defining a first area and a second area with a boundary area therebetween on a semiconductor substrate; PA1 forming a first electronic element on the first and second areas; PA1 forming a second electronic element only on the first layer; PA1 forming a first conductive layer extending from the first area to the boundary area; PA1 forming a first insulating layer entirely on the substrate; PA1 removing the portion of the first insulating layer that covers the first area, and thereby, exposing the first conductive layer; PA1 forming a second insulating layer entirely on the substrate; PA1 selectively removing the first and second insulating layers to form a throughhole; and PA1 forming a second conductive layer extending from the first area to the second area. PA1 a semiconductor substrate 301; PA1 a memory cell area "A" and a surrounding area "B" having the uppermost surface located on a level lower than that of the memory cell area; PA1 a band pattern layer 326 located on a level lower than the uppermost surface of the memory cell area "A" and disposed on a boundary area "C" provided between the memory cell area "A" and the surrounding area "B"; PA1 a first insulating layer 328 formed on the uppermost surface of the surrounding area "B" and covering the periphery of the boundary area "C"; and PA1 a second insulating layer 331 entirely covering the first insulating layer 328, the memory cell area "A" and the boundary area "C". PA1 forming a memory cell in a first area "A" of a semiconductor substrate 301 and a surrounding circuit 319 in a second area "B" of the semiconductor substrate, the latter having a height smaller than the memory cell (FIGS. 7A, 7B); PA1 growing an etching stopper layer 326 entirely on the substrate 301 (FIG. 7C), and thereafter, selectively removing the portion of the etching stopper layer 326 that covers the surrounding circuit 319 (FIGS. 7C, 7A, 7B); PA1 growing a first insulating layer 328 entirely on the substrate 301, and thereafter, forming on the first insulating layer 328 a mask 329 having a pattern overlapping the surrounding circuit 319 and the periphery of the etching stopper layer 326 (FIG. 7D); PA1 etch-removing the portion of the first insulating layer 328 that is exposed through the mask pattern 329, and thereby, exposing the etching stopper layer 326 in the first area "A" (FIG. 7E); PA1 selectively removing the portion of the etching stopper layer 326 that is not overlapped by the mask pattern 329 but is exposed (FIG. 7F); and PA1 exfoliating the mask 329 (FIG. 7G), and thereafter, depositing a second insulating layer 331 entirely on the substrate (FIG. 7H). PA1 a semiconductor substrate having a memory cell area containing a memory cell composed of a capacitor element, and a peripheral circuit area obtaining a peripheral circuit for controlling the memory cell; PA1 an insulating layer covering the peripheral circuit area and being absent in the memory cell area; PA1 protective layers covering the top surfaces and side surfaces of word line conductor patterns and bit line conductor patterns in the memory cell area; PA1 a contact hole having a circumference defined by one of the protective layers that covers the side surfaces of the word line conductor patterns in the memory cell area, the contact hole extending to a diffused region in the semiconductor substrate; and PA1 a storage electrode of the capacitor element being connected to a diffused region through the contact hole. PA1 (A) forming a field oxide layer on a semiconductor substrate to define thereon a memory cell area in which a memory cell composed of a capacitor element is formed, and a peripheral circuit area in which a peripheral circuit for controlling the memory cell is formed; PA1 (B) forming, on the semiconductor substrate including the memory cell area and the peripheral circuit area, a word line conductor pattern having a top surface covered with a first protective layer; PA1 (C) forming a pair of diffused regions in the semiconductor substrate by diffusing an impurity thereinto, using the word line conductor patterns and the first protective layer covering the top surface as a mask; PA1 (D) forming a second protective layer covering the side surfaces of the word line conductor pattern; PA1 (E) forming a first insulating layer on the semiconductor substrate including the word line conductor layer and the diffused regions; PA1 (F) selectively removing the first insulating layer by etching in the memory cell area while leaving the word line conductor layer unremoved together with the first protective layer and the second protective layer covering the top surface and the side surfaces of the word line conductor layer and simultaneously forming a first contact hole having a circumference defined by the second protective layer covering the side surfaces of the word line conductor layer, the first contact hole exposing a counterpart of the pair of diffusion regions in the memory cell area; and PA1 (G) forming, in the memory cell area, a capacitor element composed of a storage electrode filling the first contact hole and being connected therethrough to the counterpart of the diffused regions, a counter electrode, and a dielectric layer effecting insulating and isolation between the storage electrode and the counter electrode.
A further disadvantage is that the heat treatment temperature is rigidly limited because the wiring is formed of aluminum or other materials having a low melting point.
As described above, the complete flattening of the wiring is a very difficult technological problem and is still under development, i.e., it is not applicable to memory devices and the like in practice.
The production of high integrated DRAMs has the following difficulties, as described in Japanese Unexamined Patent Publication (Kokai) No. 5-299599, for example. High integrated DRAMs unavoidably require an increased height of capacitor electrodes to provide an increased memory cell capacity, resulting in a significantly increased difference in height between a memory cell area and a peripheral circuit area. Moreover, because high integration involves refining of device patterns, the focus depth allowance in a photolithography is decreased when forming conductor patterns extending across the memory cell area and the peripheral circuit area. The combined increased height difference and decreased focus depth allowance causes significant difficulty in forming the conductor patterns.
To eliminate the difficulty, the above-recited Japanese Unexamined Patent Publication (Kokai) No. 5-299599 proposed a process in which, after a memory element or capacitor is formed, a first insulating layer remains in a peripheral circuit area and a second insulating layer is then formed to fill a boundary region between the memory cell area and the first insulating layer.
The proposed process, however, disadvantageously requires additional steps including a photolithographical process so that the first insulating layer selectively remains in the peripheral circuit area alone, which unavoidably raises the production cost.
K. Sagara et al., in "1992 Symposium on VLSI Technology Digest of Technical Papers", pages 10-11 proposed a "recess structure" as another solution to reduce the difference in height between a memory cell area and a peripheral circuit area, in which the level of the semiconductor substrate is preliminarily lowered in the portion in which a memory cell array is formed.
Also in this case, however, additional photolithographical process steps are necessary to reduce the height of a memory cell array, which consequently raises the production cost. Moreover, there is also a disadvantage that field oxide layers, gate electrodes, bit lines, etc., must be formed by patterning over the preliminary formed memory cell area having the reduced height and the peripheral circuit area having an ordinary height, so that the focus depth is reduced by the height difference preliminarily provided.